Time-to-Digital Converter IP-Core for FPGA at State of the Art

The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time-Mode (TM) almost unfeasible. In particular, in Logic (PL) devices, FPGAs, operation logic is usually synchronous with system clock. However, it can happen a very high-performance specifications demands to abandon this paradigm and follow an implementative solution. main driver forcing use programmable solutions instead tailored Application Specific Integrated Circuits (ASIC), best suiting design, request coming from research community industrial R&D fast-prototyping at low Non Recursive Engineering (NRE) costs. For instance case high-resolved Time-to-Digital Converter (TDC), signal clocked some hundreds MHz implemented FPGA allows implementing TDC resolution ns. If higher required, frequency cannot be increased further one aces up designer's sleeve propagation delay order quantize time intervals by means so-called Tapped Delay-Line (TDL). This TDL-based FPGAs requires special attention designer both making all available resources foreseeing how signals propagate inside these devices. paper, we investigate TDL-TDC addressed 28-nm 7-Series Xilinx FPGA, taking into account comparison between different technological nodes 65-nm 20-nm. context, term extended dynamic-range (up 10.3 s), high-resolution single-shot precision 366 fs 12 ps r.m.s respectively), differential integral non-linearity 250 2.5 multi-channel capability 16).